As transistors disposed on integrated circuits (ICs) become smaller, transistors with source/drain extensions have become more difficult to manufacture. As critical dimensions shrink, forming source and drain extensions becomes very difficult using conventional fabrication techniques. Conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because of dopant diffusion. The diffusion often extends the source and drain extension vertically into the semiconducting channel and underlying layers, while the use of alternative channel materials such as silicon-germanium or III-V materials may enhance dopant diffusivity, degrading resultant junction profiles. Highly scaled, advanced transistors benefit from precisely defined junction profiles and well-controlled gate overlap geometry to achieve well-behaved short-channel characteristics. Positioning the junction correctly with respect to the gate is challenging. Therefore, it is desirable to have improved and controllable methods of fabrication to address the aforementioned challenges.